Sets or returns configuration and control data
| RES1_1 | Reserved, RES1 |
| USERSETMPEND | Determines whether unprivileged accesses are permitted to pend interrupts via the STIR |
| UNALIGN_TRP | Controls the trapping of unaligned word or halfword accesses |
| DIV_0_TRP | Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero |
| BFHFNMIGN | Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 |
| RES1 | Reserved, RES1 |
| STKOFHFNMIGN | Controls the effect of a stack limit violation while executing at a requested priority less than 0 |
| DC | Enables data caching of all data accesses to Normal memory `FTSSS |
| IC | This is a global enable bit for instruction caches in the selected Security state |
| BP | Enables program flow prediction `FTSSS |